« Back 20. RPi GPIO Multiplier

Top Layer 53.8 × 17.8 mm

Bottom Layer 53.8 × 17.8 mm

©2016—2025 Andrew Gillard — This site on github

Built using pcb-stackup, gerber-to-svg, svg-pan-zoom, svg2png and inspired by tracespace

PCBs designed with KiCad, to be fabricated by OSH Park, with optional solder paste stencils from OSH Stencils